Computers are entering post-Moore era, where the number of transistors on a processor chip no longer doubles every 18 months. However, the need for more powerful machines is ever increasing. The performance of supercomputing systems may be significantly improved by choosing appropriate topologies of interconnect networks.
The interconnect topologies of computational clusters are traditionally designed as fat tree topologies or vertex-symmetric graph topologies. Fat tree topologies enable simulation of any topology in poly-logarithmic time. Vertex-symmetric graph topologies are a compromise between performance and general purpose application of an interconnect network. How can we find topologies that are tailored for particular computational problems?
My research attempts to address that problem in two steps. First, by designing a virtual computational cluster that enables easy interconnect network rewiring. Second, by using that cluster to adapt the virtual interconnect network to the traffic patterns of computational problems running on it. This way I seek to find interconnect topologies tailored to particular computational problems.
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